Unbound atoms naturally attract or expel electrons forming ions. In general, metal atoms lose electrons most readily becoming positive ions, while nonmetals prefer to gain electrons becoming negative ions. Atoms joined together as molecules can also possess net positive or negative charges. These atoms are called dipoles. Atoms because they contain a positive nucleus and a negative electron cloud can become polarized in an electric field; the atoms in this state are also usually referred to as dipoles. In an electric field the atom can be thought of as possessing two superimposed positive and negative charged regions. Upon the application of the electric field the positive charge nucleus moves in the direction of the applied field and the negative charged electrons move in the opposite direction. If the electric field is strong enough, an electron may be stripped from the atom creating a positive ion, in which case the atom will migrate toward a negative charged electrode. Each element has a different ionization enthalpy, which is the energy required to remove an electron from one mole of gaseous atoms or ions.
Material sandwiched between a positive and negative charged plate can also become polarized. In this application the material between the plate is called a dielectric. Induced positive and negative surface charge densities form within the dielectric nearest to the plates, a positive region near the negative plate and a negative region near the positive plate. The distance between the plates is limited by the electric discharge that could occur through the dielectric medium. The maximum voltage that can be applied between the plates is dependent on the strength of the electric field or the dielectric strength of the dielectric. The dielectric by nature reduces the electric field potential between the charged plates or probes. If the field strength in the medium exceeds the dielectric strength the insulating properties break down and the medium begins to conduct. Every substance has its own unique dielectric strength. An electric field created between two oppositely charged very sharp tip probes, unlike the charged plates, is not uniform, but weakens along a radius perpendicular to a imaginary line connecting the centers of the probes tips. The maximum electric field potential lies at the tips of the probes. Therefore, the maximum surface charges created by the electric field are found on the dielectric underneath the probe tips.
The process of moving elements through a liquid medium from one charged inert electrode to a second oppositely charge inert electrode is called electrolysis. If the electrodes participate in the electrolysis process one electrode may dissolve and plate the other. This deposition of one electrode onto another is commonly called electroplating. The movement of ions in a solution can be used as a technique as shown by Dr. Jean-Claude Bradley in his published articles appearing in Nature (1997, vol. 389, p.268) and Advanced Materials in December 1997 (vol. 15, p. 1168) to create micro wires and micro wire connections between circuits. In his procedure two thin copper plates are placed between two inert highly charged electrodes. The electrodes induce opposite surface charges on the copper plates. The surface charges create copper ions that travel across a substrate from one plate to the other. Because of gravity and Brownian motion of the medium the ions slow down and deposit on a surface between the copper plates. The ions deposited between the plates form a non-conducting wire type pattern. To make the wire conductive the pattern is placed in a copper plating solution for a set time.
Dr. Bradley's technique is called Spatially Coupled Bipolar Electrochemistry (SCBE), because the method avoids physical contact with the devices three-dimensional circuitry can be created. His technique is also used to form functional catalysts in which the positioning of catalytic materials can be precisely placed on isolated particles a few microns wide allowing for the creation of designer catalyst that can be used in commercial and industrial applications.
Another technique to manipulate neutral atoms is by creating standing electromagnetic waves positioned on top of a substrate in a vacuum to focus neutral atoms into linear or dot patterns by dipole force interactions, as shown in U.S. Pat. No. 5,360,764, issued to Celotta, et al. This process which also works for ions is designed to create evenly spaced groups of linear or spotted patterns for semiconductor devices. To create single lines or dots, a filter or mask is used to block the unwanted material. The process works since atoms of different elements will only absorb photons with a specific energy. Because of this a group of tunable lasers can be set to a frequency just below the atoms abortion frequency so that the atoms will not absorb the photons. Instead the photons will interact with the atom and change the atom's momentum slowing it down. This procedure is called laser cooling. The use of multiple lasers can actually trap atoms in a suspended state. The 1997 Nobel Prize in physics was awarded jointly to Steven Chu, Claude Cohen-Tannoundji and William D. Phillips for the development of methods to trap and cool atoms.
In current fabrication of integrated circuits at any scale, an opaque mask or reticle with a desired pattern is created to block light usually infrared, or an electron beam from exposing a photon or an electron beam sensitive resist placed on top of a substrate. In the fabrication of integrated circuits the substrate is a semiconductor. In the creation of micro machines the substrate can be any dissolvable material from which the part can later be freed. After exposure the exposed area of the resist is then removed, if a positive resist is used, a void will be created. In the creation of semiconductor devices the void is filled with a selected doping material. The dopants most readily used are phosphorous pentoxide or boron nitride. After the dopant has been placed on the silicon it is placed in a furnace with temperatures between 950 and 1000 degrees Celsius. The dopant, because of the high temperature, will diffuse into the substrate. The dopant concentrations, depth, and distribution in the substrate are mostly unpredictable.
Silicon dioxide can also be formed on the substrate acting as insulation between a silicon substrate and the interconnecting wires. The silicon dioxide is formed at 1100 degree Celsius temperatures. During the formation of silicon dioxide the surface silicon is being consumed. The final stage is connecting the wires and annealing them at 475 degrees Celsius. These steps are usually repeated a few times to create integrated circuits or a micro machine. The size of the device is dependent on the wavelength of the resist exposing particles, the smaller the wavelength the greater the resolution.
In a semiconductor wafer the electrically active area is only 10 microns deep which is usually only 1% the thickness of a typical wafer used in commercial applications. If energetic short wave particles like x-rays or elections are used to expose the resist to achieve greater resolution, they can destroy the surface of the substrate. Furthermore, if the substrate is a semiconductor unknown defects in crystalline structure can form allowing for unwanted and unpredictable variations in the devices electrical properties through the thin shell in which the current flows. This can hamper the goal for current fabrication, which is to create micro devices as small and defined as possible. The more devices that can be fitted onto a single surface will reduce the cost, the delay in switching, and the power consumption of the device (up to a physical point).
In 1986 Gerd Benning and Heinrich Rohrer who shared the Nobel Prize in 1986 with Ruska created the scanning tunneling microscope, STM. STM works by placing a tungsten probe with a tip with a width of an atom held between 0.1 and 1 mm over a conducting surface. An electron tunneling current flows through a vacuum between the tip and the conducting surface of the substrate when a potential difference is applied. As the probe moves across the substrate and the tunneling current changes as the distance between the probe and surface changes, an image of the surface can be created with the required devices. In this imaging technique horizontal resolution is about 0.1 nm and vertical resolution is about 0.001 nm.
If the potential is increased between the probe and substrate, surface atoms can be vaporized from the surface. This is shown in U.S. Pat. No. 4,896,044 issued to Li, et al. The current can only last about 200 microseconds, if a longer duration is used the material and substrate may melt locally. This technique can only be used for conducting surface materials and like electron beam lithography could harm the substrates underlying atomic structure.
In another technique using an "Electrochemical STM". A sharp probe and conductive surface are submerged in a highly concentrated electrolyte consisting of copper sulfate and sulfuric acid, as shown in Dr. Rolf Schuster's published article appearing in, Physical Review Letters, 80,5599 (1998). A 60-nanosecond pulse of voltage is further applied between the needle and substrate, creating a pit in the surface of the substrate 5 nm in diameter and with a 0.3 to 1 nm depth. By reversing the voltage copper ions in the electrolyte can be deposited on the substrate, creating 1 nm high by 8 nm diameter formations. In this set up ultra-short pulses must be used, if not micrometer size modifications are created. This is due to the spreading of the electric fields from the probe's tip along the charged substrate's surface to its ends. With a short pulse, the electric field created interacts with the area underneath the probe's tip quickly enough so that the areas surface charge is not weakened locally. Because of this the electric field does not have the time to widen creating a larger formation or pit.
Another technique is shown in U.S. Pat. No. 5,478,698 issued to Rostoker, et al., in which the electrons emanating between the probe and surface exposes an electron beam resist. Nano-patterns can also be formed on an insulating material, as shown in U.S. Pat. No. 5,042,649 issued to Hodgson, et al. Currently various forms of STM's are being used to create nano-sized patterns on electron beam sensitive resists to be used in traditional lithography processes.
There are some problems in current integrated circuit fabrication that are not a major issues currently, but are going to become more relevant as devices get smaller. The first problem is to make smaller devices. In the traditional lithography process the transparent resist used in the traditional mask can not be exposed using extreme ultraviolet light, which is light with a wavelength below 150 nm. Currently lithography manufacturers are starting to use 193 nm ArF lasers. As illustrated above, using the STM may solve this problem, but unlike lithography techniques, STM's can only create the patterns on a chip one at a time, making STM resist exposing very slow and expensive.
The second problem is that as the interconnect wires between transistors get smaller the resistance and capacitance of the circuit increases which creates delays in data transfer.
Finally, another major problem is the heat generated from the formed chips, as they get smaller their power consumption increases as well as the operating electrical currents which can be as high as 50-amps, therefore increasing the device's operating temperature. As the temperature of the device increases, errors and possible diffusion among the material patterned on the device increases. Currently, copper interconnects are begging to be used instead of traditional aluminum interconnects, since copper has a better resistance than aluminum. Copper, like aluminum, will eventually reach its limit. For this reason new and novel devices must be created.
Gallium arsenide (GaAs), and a few other semiconductor materials are traditionally used in the formation of light emitting diodes (LED's) and detectors in conjunction with optical fiber interconnects to transfer data between two devices and between individual computer chips, eliminating the need for traditional copper wire data transfer interconnects. The advantages of GaAs and fiber optic devices is that data transfer between two computer chips is less restrictive and faster, eliminating most of the problems associated with current and future integrated device designs. A fiber optic line (or wave-guide as sometimes called) is made from glass, crystalline, polymeric, or plastic materials. Each optical material has its own degree of transparency and refractive index. Plastic and polymeric fibers are the cheapest to manufacture but are traditionally the worst optically. Haze and birefringence are inherent to plastics. Plastics also have large variations in their refractive index with changes in temperature.
A fiber optic wire is usually made of one dielectric material called the core surrounded by a second dielectric material with a smaller refractive index called the cladding. Electromagnetic energy entering the fiber is then confined by the phenomenon of total reflection caused by the differences in the refractive index of the two dielectrics. In integrated optics the core is created by ion implantation or diffusion, creating a region with a higher index of refraction within the original material.
The problem associated with the formation of optical interconnects or any optical device is that the creation of optical interconnects is an expensive and fragile process. As an example, the above GaAs interconnect is formed by cutting the GaAs LED's into small squares and using precession machinery placing the cut squares on a silicon chip. The LED's are then bonded to the pre-fabricated silicon circuit, the technique being very time consuming. Optical fibers are then bonded to the LED's and to photodiodes on the associated chip. The optical interconnects, because of their data transfer speed, create the illusion that the devices at the ends of the fiber optic line are located next to each other. This is important in the transfer of data between the processor, the registers, and memory. The farther away a memory source is, the longer the data transport time to the registers.
A simple fix which is currently being used is to place as much memory (L1 cache) on the same chip as the processor. However, by doing this, the cost of the manufacturing of a chip increases since the possibility of fab errors and the die size increase. Therefore, processor manufacturers usually opt to put as much memory as they can afford on the processor chip, and place the extra memory called secondary memory (L2 cache) off the main processor. Having two chips decreases the fabrication cost by using two smaller dies therefore reducing fab errors, but it also decreases the speed of data transfer, called memory latency. By using optical interconnects instead of standard copper wires, the delay time is significantly reduced, but as with adding more L1 cache the process increases the total cost of the chip.
Wave-guides can also be used to perform logic operations, switching, and modulation. This is accomplished by bringing two parallel wave-guides in close proximity and applying a stress to the area. The refractive index of the wave-guides, surrounding, or the connecting material are altered allowing signals to cross over between two parallel wave-guides or to change the phase of the light wave along one of the wave-guides, to create logic devices as shown in U.S. Pat. No. 5,150,242 to Fellows. It is also used in Mach-Zehnder interferometers and directional couplers as shown in U.S. Pat. No. 5,502,781 to Li, et al. The disadvantages of using wave-guides are that for operations to be performed the wave-guides may be a few centimeters long. This takes up valuable space on a two dimensional chip. An another disadvantage is the lossiness of each operation or cross over. Lossiness is the leaking of light out of the wave-guide into the surrounding medium, which weakens the signal. The lossiness can be lessened by many techniques. One example is using optical amplifiers as shown in U.S. Pat. No. 5,007,698 by Sasaki, et al. Logic operations can also be accomplished without wave-guides as shown in U.S. Pat. No. 5,159,473 to Feldman in which spatial light modulators and computer generated holograms create logic operations using free waves, where constructive or destructive interfering beams are formed on top of properly positioned detectors. The use of free wave optical computers have advantages over wave-guide driven computers, but free wave optical computers require precise aliment of the components unlike wave-guide driven optical computers, which are coupled, directly from a light source to a detector.
In 1990 it was discovered that porous silicon had photoluminescence properties. In 1992 it was further discovered that if a current is applied to porous silicon it emits light. Because of this, less expensive silicon based computers and devices can be created using light as an information carrier. Currently, formation of porous silicon is done by stain etching or local anodization. The goal in the formation of porous silicon is creating pores that are uniform in size, shape, and distance apart, to better control its light producing and detection properties. The advantage of porous silicon is that it is much cheaper to form than the traditional optical semiconductors like GaAs.
To keep Moore's Law true, the computer industry must eventually switch from traditional design techniques to new manufacturing processes. A need is then not only to find and implement these new techniques to develop smaller and faster IC's, but also more importantly to create techniques to form newer, smaller, and less expensive electro-optical and pure optical devices.